Open Access

Daniel Pedder

• This Bachelor thesis examines how the security of a hardware Advanced Encryption Standard (AES) implementation can be influenced at both pre- and post-synthesis levels. At pre-synthesis level, side-channel vulnerabilities are analysed using Simple Power Analysis (SPA). Countermeasures are implemented into the design, which significantly improve SPA results in pre-synthesis simulation, but prove less effective in post-synthesis layout simulation. This study then explores how different post-synthesis layouts and data variations affect Differential Power Analysis (DPA) results. Layouts synthesised with the same Process Design Kit (PDK) are compared based on their DPA results to evaluate the influence of layout variations on DPA results. Then, the same layout is tested with identical or different data inputs, to analyse the impact of data variations on DPA results. Overall, variations in DPA results are minimal, suggesting that layout or data variations have little impact on side-channel robustness. Lastly, the influence of PDK choice on DPA results is examined by synthesising the AES design with different PDKs. Despite variations in layout size and toggle behaviour, no conclusive relationship between PDK choice and DPA resistance is identified. These findings indicate that post-synthesis optimisations have only a small impact on side-channel security, showing the need for pre-synthesis countermeasure implementation.